1. Field of the Invention
The present invention relates to a debug system and method, and more particularly to a POST (power on self test) debug system and method which can be applied to electronic devices such as server systems.
2. Description of Related Art
On startup of a server system, a central processing unit (CPU) reads routines stored on a BIOS (basic input output system) chip of the motherboard for initializing hardwares within the server system. Through the routines, registers of the CPU are tested first and then peripheral devices such as a dynamic random access memory (DRAM), a motherboard chipset, a display card and so on are initialized. The initialization of the hardwares includes adding values to registers or changing register values according to some specific technology files such that chipset memory, I/O functions and so on can operate normally.
However, some errors such as hardware errors or BIOS routine errors may occur during the initializing process. Such errors can lead to fail operation of the server system. Since the BIOS routine code is small in size and the operation system (OS) has not been loaded to the server system during the initializing process, it is impossible to use large size debug software for debugging. Instead, a user only can search errors from original codes or use some specific devices for debugging hardware at a rather low speed.
To overcome the above defect and increase the debug speed, a plurality of I/O ports is defined as debug ports such as Ports 80H, 84H and 85H. During a power on self test, while a certain POST routine is executed, a POST code value corresponding to the routine will be sent to a port such as port 80H I/O. Through a specific debug peripheral device such as a POST card, the post code value can be acquired and displayed. The POST code will be kept without being changed until the next POST routine is executed. Thus, before an operation system is loaded, a user can find reason for error through the post code value displayed by a debug peripheral device such as a POST card.
However, the above debug system needs a POST card having a decode circuit for decoding the POST code and a display means such as a LED for displaying the debug status, thereby increasing the debug cost. Further, both a PCI slot for receiving the POST card and the LED need to be disposed on the motherboard, which thus limit the motherboard layout flexibility. Furthermore, when the server system begins to reset because of some errors of the routines, the POST code value is easy to lose, which accordingly increases the debug difficulty for developers.
Although combining an ISA bus or a LPT bus with a POST card is also possible for system debugging, such a method is rather complex and difficult to implement.
Accordingly, there is a need to develop a POST debug technology which can overcome the defects of the conventional technology.